KiCad — PCB Layout

🔴 The unit that prevents most of the confusion beginners have with KiCad, and it is almost always skipped. KiCad is several editors over a set of loosely coupled files, and the relationship between them is explicit rather than magic: a symbol is not a footprint, the schematic does not contain the board, and the link between them is a named association you control. Understanding that structure up front turns a whole category of 'KiCad did something weird' into 'I edited the wrong file'.

The second-biggest source of avoidable pain, and the one that only bites once you share a project or move machines. Library tables, the difference between a global library available to everything and a project library that travels with the design, and path substitution variables. The failure mode this unit prevents is concrete and common: a project that opens perfectly on the machine it was drawn on and shows missing footprints everywhere else.

Drawing the design once you know what you are drawing. Placing and annotating symbols, wires versus labels versus buses, hierarchical sheets for anything non-trivial, and the power-flag idiom that exists purely to satisfy the rule checker. A Skill element because schematic legibility is a craft — a correct schematic that nobody can read is a real defect, and it is only trained by drawing and being critiqued.

Every real design needs a part the libraries do not have. Drawing a symbol with sensible pin types and electrical roles, choosing pin numbering that matches the datasheet rather than the drawing, and then the association step that binds it to a physical footprint. This is the unit where a mistake is cheapest to make and most expensive to find — a wrong pin mapping survives every check the tool performs and appears at bring-up.

Running ERC is trivial; interpreting it is not. The checker validates pin-type compatibility and connectivity, which means it catches unconnected inputs and conflicting outputs and is completely blind to a net that is connected to the wrong correct-looking thing. This unit is as much about the checker's blind spots as its output, because trusting a green ERC is a documented route to a dead board.

Where the design meets a real assembly process. Pad geometry from the manufacturer's recommendation, courtyard and silkscreen conventions, mask and paste layer control, and the wizard-generated footprint that is correct in shape and wrong in the detail that matters. Attaching 3D models belongs here too — mechanical interference is far cheaper to find in the viewer than in the enclosure.

🔴 Done before layout, not after, and doing it after is the most common workflow error in the tool. The stackup, net classes, clearance and width rules and via definitions are the constraints the interactive router then enforces for you. Set them first and the router keeps you legal while you work; set them last and you get a design-rule report with several hundred violations and no good way to fix them.

The theory path argues that placement is the decision every later stage inherits; this unit is about executing it in KiCad. Cross-probing between schematic and board, grouping by function, working with the ratsnest as a placement quality signal, mechanical constraints and board outline, and locking down what must not move. Judgement content, so it is trained by critique of real placements rather than by recall.

The interactive router and what its modes actually do — walk-around, push-and-shove and highlight-collisions are three different mental models, and picking the wrong one for the situation is most of the frustration people report. Then differential pairs, length tuning, and via placement. Fluency here is measurable and it matters: routing is where the hours go, and the difference between fluent and hunting is several times the total design time.

Copper pours are where the tool's behaviour and the electrical theory are most easily out of step. Zone priority and fill rules, thermal reliefs on pads and why they exist, keepouts, island removal, and the split plane that silently severs a return path the schematic says is intact. The unit exists because a filled pour looks like a solid plane on screen regardless of whether it is one.

DRC verifies the board against the constraints entered in unit A7 — which means a clean DRC proves your board matches your rules, and nothing at all about whether your rules were right. Covers the checks worth adding beyond the defaults, custom rules for the cases the built-in set does not express, and the unconnected-item report that is the actual safety net.

The deliverable, and the point at which mistakes become physical. Gerber and drill generation with the settings vendors expect, the newer single-file interchange format and when to use it, component position files, and a bill of materials the assembler can actually source from. Includes reading your own output back in a viewer before sending it, which is the one check that catches layer and origin errors.

What actually happens to your files at the fab and the assembly house, and what gets a job rejected or silently altered. Capability limits, panelisation, the engineering queries you will receive and what a sensible answer looks like. The Risk element is commercial rather than physical, and it is real: an unnoticed change made on your behalf, or a tolerance you did not specify, arrives as a box of unusable boards weeks later.

The capstone and a Skill element by construction — an artifact, not an answer. One real board taken all the way through: schematic, library parts, placement, routing, checks, outputs, and a design review of your own work before it is sent. Nothing about this unit can be closed by a quiz.

Last because it only pays once the workflow is familiar. KiCad's file formats are text and its Python interface is real, which makes generated layouts, automated checks and meaningful diffs possible in a way most EDA tools do not allow. This unit is what turns KiCad from a drawing program into part of an engineering pipeline, and it is genuinely differentiating on a portfolio.